1. Field of the Invention
The present invention relates to recovery of integrated circuits comprising microprocessors (or microcontrollers) which have received an electrical transient voltage resulting from an electrostatic discharge occurring during normal operations or during electromagnetic compatibility testing.
2. Description of the Related Art
Electrostatic discharge (ESD) includes: (1) a localized transfer at the discharge point; (2) inductive coupling between a higher voltage or xe2x80x9cchargedxe2x80x9d object and the discharge object; and (3) electromagnetic radiation from the charged object.
To initiate the correct operations of a microprocessor, a power-on reset circuit is often incorporated within the device to send reset signals to reset the microprocessor to a known state and thus permit execution of the normally desired functions. The failure to power-up in a known state can cause an integrated circuit to function unpredictably. Such unpredictability is particularly undesirable for microprocessors used in, for example, computer keyboards. The following list of U.S. patents and publications provide background information regarding prior art power-on reset circuits; these documents are incorporated by reference herein:
[1] S. R. Norsworthy, xe2x80x9cCMOS Power-Up Reset Circuit for Gate Arrays and Standard Cells,xe2x80x9d U.S. Pat. 4,633,107, December, 1986.
[2] C. C. Hanke, C. D. Obregon, and T. W. Sutton, xe2x80x9cCMOS Power-On Reset Circuit,xe2x80x9d U.S. Pat. No. 4,970,408, November, 1990.
[3] R. C. Steele, xe2x80x9cPower-Up Reset Circuit,xe2x80x9d U.S. Pat. No. 4,983,857, January, 1991.
[4] K. L. Wong and J. D. Schutz, xe2x80x9cPower-Up Reset Circuit,xe2x80x9d U.S. Pat. No. 5,111,067, May, 1992.
[5] A. Yukawa, xe2x80x9cPower-On-Reset Circuit,xe2x80x9d U.S. Pat. No. 5,136,181, August, 1992.
[6] S. Tanimoto, xe2x80x9cPower On Reset Circuit with Accurate Detection at Low Voltages,xe2x80x9dU.S. Pat. No. 5,485,111, January 1996.
[7] G. L. Geannopoulos, xe2x80x9cPower Up Reset Circuit with Threshold Voltage Shift Protection,xe2x80x9d U.S. Pat. No. 5,654,656, August, 1997.
[8] C. McClintock and N.Ngo, xe2x80x9cPower-On Reset Circuit with Well-Defined Reassertion Voltage,xe2x80x9d U.S. Pat. No. 5,821,787, October, 1998.
Known prior art power-on circuits can generate a reset signal to initiate the reset of the microprocessors. The main design principle of such power-on-reset circuits is that a time delay concept is used to generate a reset signal pulse when the integrated circuit is in a power-up or transition phase. Some designs have a low-voltage-detection function, whereby the power-on reset circuits can detect a VDD voltage level drop and subsequently generate another reset pulse to reset the microprocessors. However, such prior art power-on-reset circuit designs are able to detect only low-speed VDD derivations in a time period on the order of milliseconds (ms).
Accordingly, so long as the voltage level of the VDD changes over a time period on the order of ms, the prior art power-on-reset circuits can perform adequate detection of the voltage transition required to reset a microprocessor. However, such prior art power-on-reset circuits cannot detect voltage transitions that occur over a shorter period of time on the order of nanoseconds (ns).
Significantly, the electromagnetic compatibility (EMC) verification of electronic products, such as the system-level ESD (electrostatic discharge) test (so-called xe2x80x9cESD zappingxe2x80x9d), the monitor arcing test, and the EFT (electrical fast transition) test, often generate electrical pulses with a time scale on the order of nanoseconds (ns). The standard to verify the system-level ESD test is the xe2x80x9cIEC 801-2, Electromagnetic Compatibility for Industrial Process Measurement and Control Equipment, Part 2, Electrostatic Discharge Requirements,xe2x80x9d 2nd Edition, 1991. The standard to verify the EFT test is the xe2x80x9cIEC 1000-4-4, xe2x80x9cElectromagnetic Compatibility (EMC), Part 4, Testing and Measurement Techniques Section 4, Electrical Fast Transient/Burst Immunity Testxe2x80x9d 1st Edition, 1995. Such fast electrical pulses (also referred to as fast electrical transient voltages) can couple into the internal circuits of a microprocessor through an inductance or capacitance coupling and interfere with the operating instructions temporarily stored in the registers, flip-flops, or RAM of the microprocessor.
When the logic states stored in the registers are changed by a coupled fast electrical pulse, the information stored in the registers may become unintelligible. Furthermore, parity values may no longer match because of corruption of the data. If the corrupted logic states are part of a critical function of the microprocessor, it is likely that the microprocessor will, as commonly referred to in the industry, xe2x80x9clock up,xe2x80x9d xe2x80x9cfreeze,xe2x80x9d xe2x80x9chang,xe2x80x9d or go into a xe2x80x9ccontinuous loop,xe2x80x9d while unsuccessfully attempting recovery. It is even possible that a corrupted logic state in the microprocessor caused by a fast electrical pulse may not be discovered until some time afterward when conditions dictate use of those circuits having corrupted logic states. Sometimes, only a complete power-on-reset (which is disruptive to the user) will totally reset all of the latches.
Many products are now being tested for their susceptibility to damage from electrostatic discharge. These electromagnetic compatibility tests may also cause unsuspected problems on the units selected for test. In fact, EMC testing can lead to equipment destruction, yet every circuit during and after the EMC test may remain within the specifications with no apparent permanent parameter changes. However, it is more common that the microprocessor can become upset and/or the electrical system can be frozen after the EMC tests. Most such microprocessors can be restored if the power supply is reset again. However, the executing functions or operating steps of the microprocessor are also reset. In most automated controls for important applications, resetting of the power supply is not an acceptable solution to overcome a detected transient voltage. Therefore, after experiencing electrical interference due to the electromagnetic compatibility verification tests, the microprocessors must recover by themselves without restarting the power supply to achieve an acceptable rating.
Even if an 8-bit microprocessor can sustain a component-level ESD stress of greater than 5 kV , keyboard upset and operational errors have been found in the system-level ESD stress with a 2 kV ESD voltage in the contact-discharge testing method. To meet this system-level ESD specification, some discrete components (such as a magnetic. core, ferrite beads, and RC low-pass circuits) are added into the keyboard circuit board to absorb or bypass the electrical transient due to the system-level ESD test, as shown in the prior art design of FIG. 1.
FIG. 1 shows a prior art system that absorbs or bypasses the transient voltages by including a series of discrete hardware circuits connected to microprocessor 1. Ferrite beads 2 are connected to VDD 3 and to VSS 4. An RC network may also be employed. A series of capacitors 5 coupled to the lines containing the ferrite beads 2 or the resistors 2a provide a high frequency short to VSS so that high frequency transient voltages are bypassed. Low frequency voltages representing digitized information pass freely. The keyboard cable 6 comprises a group of current carrying wires that are wrapped around a magnetic core 7 and then connected to the ferrite beads 2 and resistor 2a. A high frequency voltage transient will be dropped across (i.e. absorbed by) magnetic core 7 to protect the microprocessor 1 from a transient voltage traveling down the keyboard cable. Some of the drawbacks to this prior art system include the requirement for expensive and bulky discrete components such as the magnetic core and ferrite beads.
Another prior art power-on-reset circuit is disclosed in reference [3]. This circuit is designed so that a logic 1 output will cause an asynchronous reset of all of the registers on the microprocessor. However, such circuits are nominally designed for a delay of the reset signal to ensure that the supply voltage and all circuits have reached stable operating voltages. The delay is often longer than the rise time of the supply voltage.
Accordingly, such power-on-reset circuits disclosed in the aforementioned background references cannot respond to fast electrical pulses. Even if the microprocessors have included such power-on-reset circuits in their chips, they still can be upset or frozen during the electromagnetic compatibility tests.
In some prior art system-level designs, extra external hardware circuits are used as a reference to verify the execution of instructions and to restore normal conditions in the microprocessors if abnormal conditions are detected. In order to prevent the keyboard from being upset or frozen after a system-level ESD zapping test, the microprocessor should have an auto-detection function in the integrated circuit (IC), so that the microprocessor can be automatically reset and restored gradually to a known and stable state. The firmware must perform a regular status check for abnormal conditions. An effective method to assist the firmware in the status check is to use an external hardware timer, such as the retriggerable monostable multivibrator, as shown in FIG. 2.
FIG. 2 shows an example of a prior art power-on reset circuit from xe2x80x9cNoise Reduction Techniques in Electronic Systems,xe2x80x9d H. W. Ott, 2nd Edition, John Wiley and Sons, 1988. A series of flip-flops 8 are used to provide a reset pulse on line 9 to a microprocessor (not shown) in conjunction with a change in the level of both VCC 10 and a sanity pulse on line 11. However, this method also requires extra circuits (such as a 74LS123 multivibrator) and additional components on the circuit board to assist in the recovery of the microprocessor, often increasing costs.
In other prior art designs, a hardware circuit called a xe2x80x9cWatchdog Timerxe2x80x9d is added to the microprocessor to check the instruction execution and restore the normal conditions with the cooperation of a firmware design. A Watchdog Timer remains in a reset state as long as an application or device is functioning properly. Periodically, a rest command is sent to a time delay portion of the Watchdog Timer. Should an application xe2x80x9clock upxe2x80x9d or xe2x80x9cfreeze,xe2x80x9d it will be unable to send additional reset pulses to the time delay portion. Thus, the time delay portion subsequently xe2x80x9ctimes outxe2x80x9d after a predetermined interval and opens or closes a contact which permits the reset command to be sent to reset the device.
However, the logic states of the Watchdog Timer are still stored in the registers or flip-flops, and they also may be interfered with and changed by the fast electrical pulses to cause an upset of the microprocessors. When the fast electrical pulse has a higher glitch level, the microprocessors associated with the Watchdog Timer circuits still can be frozen.
Moreover, when a fast electrical transient having a high-level voltage occurs, the logic states stored in the counters, the registers, the memory, or the flip-flops in the microprocessor are totally destroyed. Therefore, the program instructions in the keyboard may still lock-up in an infinite loop from which it can not escape, even if a Watchdog Timer has been included. The infinite loop causes the keyboard to become upset or frozen after receipt of the system-level ESD zapping. The keyboard can recover only if the hardware reset is manually restarted again. Such a manual restart is not acceptable for keyboard products certified by the xe2x80x9cCExe2x80x9d mark (CE is an acronym of the French phrase xe2x80x9cConformite Europeenexe2x80x9d). Therefore, the discrete components shown in FIG. 2, and a more complex redesign on the board layout, must be incorporated into the keyboard circuit board to absorb or bypass the electrical transient. If the keyboard is required to sustain a much higher value of system-level ESD zapping, more expensive discrete components must be used, but the keyboard operations may still become upset under some ESD testing conditions.
Moreover, a microprocessor fabricated in the scaled-down CMOS process with a much smaller die size is more sensitive to electrical transients. Additional, or larger, magnetic cores and ferrite beads are used on the keyboard circuit board to restrain the electrical transient generated from the system-level ESD test. However, such additional discrete components substantially increase the total cost of the keyboard. Therefore, a microcontroller with robust system-level ESD susceptibility for high frequency transient voltages and on-chip automatic recovery, which does not require the expensive additional discrete components on the circuit board, is strongly desired by keyboard manufacturers and the public at large.
The present invention is directed to providing an effective on-chip ESD sensor to detect system-level electrical transient voltages while enabling resumption of normal operations without a general power-on reset that severely disrupts system operation.
According to one aspect of the present invention, there is provided a device for automatic recovery of an integrated circuit after occurrence of an electrostatic discharge received by the integrated circuit, the integrated circuit comprising at least one of a microprocessor and a microcontroller and having a VDD line and a VSS line, the device being included in the chip of the integrated circuit. The device comprises an electrostatic discharge sensor means, connected between the VDD and VSS lines, for sensing an electrostatic discharge voltage, associated with the electrostatic discharge, on the VDD and VSS lines, and for generating a sensor output signal when the electrostatic discharge voltage is sensed; an electrostatic discharge flag means for, in response to the sensor output signal, outputting a flag signal indicating sensing of the electrostatic voltage by the sensor means; and control means for (i) performing a reset procedure on the integrated circuit in response to power-on of the integrated circuit and (ii) performing a recovery procedure to restore predetermined functions of the integrated circuit in response to the flag signal indicating sensing of the electrostatic voltage by the sensor means. The reset procedure can comprise a first set of operations and the recovery procedure a second set of operations which is different from the first set of operations. The second set of operations can be one of (1) a subset of or (2) an overlapping set of the first set of operations. In the keyboard, when the keyboard is upset by the system-level ESD Zapping, the original operation instruction or operating states in the keyboard can be recovered by down-loading the original states that were stored in the PC system. The sensor means can include a plurality of electrostatic discharge sensors located at a plurality of different positions within the integrated circuit, and the device can further comprise logic means for logically combining outputs of the plurality of electrostatic discharge sensors to provide a logical input to the electrostatic discharge flag means. The logic means can comprise an OR gate, a NAND gate, or other type of logic gate, and the electrostatic discharge flag means can be e.g. a flip-flop such as a D flip-flop. The plurality of electrostatic discharge sensor means can comprise a first electrostatic discharge sensor having a larger NMOS width/length (W/L) ratio than its PMOS WIL ratio and a second electrostatic discharge sensor having a larger PMOS W/L ratio than its NMOS WIL ratio.
According to the present invention, a combined hardware/firmware system automatically recovers a microprocessor during electromagnetic compatibility tests. By including special ESD sensors and an electrostatic discharge flag on-chip in the integrated circuit including the microprocessor or microcontroller, a coupled fast electrical pulse from either a system-level ESD zapping or an electrical fast transition test on the microprocessor/microcontroller can be detected.
According to an embodiment of the present invention, an on-chip automatic recovery apparatus for an integrated circuit including a microprocessor/microcontroller comprises an electrostatic discharge sensor comprising a plurality of latch logic gates, and an electrostatic discharge flag electrically connected to an output of the electrostatic discharge sensor.
According to another embodiment of the present invention, the electrostatic discharge sensor comprises two latch logic gates for detecting the system-level electrical transient voltage. The logic gates have their outputs connected to the input of an OR gate (or a NAND gate), and the output of the OR gate is connected to the input of the electrostatic discharge flag.
The number of latch logic gates can be increased for placement throughout different areas of the microprocessor for more effective ESD protection than placement at merely the input or output areas. Accordingly, the number of input lines of the OR gate should increase with corresponding number of latch logic gates.
According to yet another embodiment of the present invention, the first latch logic gate is designed so that the NMOS has a width-to-length (W/L) ratio larger than that of its PMOS to cause the latch to lock easily at logic 0. In contrast, the second latch is designed so that the PMOS having a larger W/L ratio than that of its NMOS to cause the latch to lock easily at logic 1. The firmware stored in the ROM of the microprocessor automatically checks the electrostatic discharge flag (which is typically a flip-flop such as a D flip-flop) to monitor the abnormal conditions in the system operation. If the microprocessor becomes upset or is locked up by a system-level ESD transient voltage, or by the electrical fast transition test (EFT), the microprocessor is recoverable quickly to a known and stable state.
The microcontroller having a combined hardware/firmware device is fabricated in a 0.45 xcexcm CMOS process. The system-level ESD susceptibility level of the 8-bit microcontroller used in keyboard products has been improved from an original 2 kV or 4 kV value to become greater than an 8 kV or 15 kV value, depending on whether the respective contact-discharge or air-discharge methods of ESD zapping are used.
According to another aspect of the present invention, there is provided a method of performing an automatic recovery procedure for an integrated circuit after occurrence of an electrostatic discharge received by the integrated circuit, the integrated circuit having a VDD line and a VSS line and comprising at least one of a microprocessor and a microcontroller. The method comprises the steps of starting the integrated circuit by a power-on reset sequence including setting an electrostatic discharge flag at a first logic state; sensing an electrostatic discharge voltage on the VDD and VSS lines; changing the electrostatic discharge flag to a second logic state in response to the sensing of the electrostatic discharge voltage on the VDD and VSS lines; performing a recovery procedure to restore predetermined functions of the integrated circuit in response to the flag being set in step (b) to the second logic state; and thereafter, resetting the flag to the first logic state. The reset procedure comprises a first set of operations and the recovery procedure comprises a second set of operations which is different from the first set of operations. The second set of operations can be one of (1) a subset of or (2) an overlapping set of the first set of operations.
In another variation of the above method, a plurality of electrostatic discharge sensors are employed and are located at different locations on the integrated circuit including the microprocessors/microcontroller and have their outputs tied together at an input of the electrostatic discharge flag. Another option is to employ more than one electrostatic discharge flag.
The electrostatic discharge flag may comprise a flip-flop such as a D flip-flop and the outputs of the plurality of electrostatic discharge sensors can be tied together through, for example, an OR or NAND gate. If any of the electrostatic discharge sensors change their status from logic 0 to logic 1, this change will be input to the electrostatic discharge flag by setting, for example, a flip-flop such as a D flip-flop to logic 1. The logic 1 output of the OR (or NAND) logic gate also activates the firmware recovery procedure of the microprocessor/microcontroller.
By way of overview, the present invention provides a combined hardware/firmware device and method for automatic recovery of an integrated circuit the invention avoids a disruptive power-on reset after occurrence of an electrostatic discharge which may occur during normal operations or during electromagnetic compatibility testing. The device is incorporated into the chip of the IC and includes an electromagnetic discharge sensor, a flag, and firmware to execute the recovery and reset procedures. The sensor is located between the VDD and VSS lines of the IC which itself includes one or both of a microprocessor and a microcontroller. In a power-on reset sequence, the sensor output and the flag are both set to logic 0. After an electrical transient voltage occurs, the sensor output is set to logic 1. The logic 1 output of the sensor sets the flag, which may be a flip-flop such as a D flip-flop, to a value of logic 1. When either a power-on reset operation begins or the sensor output is set to logic 1 due to an electrical transient voltage on the VDD-VSS lines, firmware begins a reset subroutine in which (1) the sensor output is reset to logic 0, (2) the status of the flag is checked, (3) if the flag is at logic 1, the firmware performs a recovery procedure to restore predetermined functions of the IC and resets the flag to logic 0 (the recovery procedure being performed on the order of nanoseconds), and (4) if the flag is at logic 0, a general reset procedure is performed. The apparatus and method permit higher levels of electrostatic discharge to be absorbed by a device without causing permanent damage and/or corrupted data. One particular embodiment for the present invention is for personal computer keyboard microcontrollers.